Logical synthesis

1) logical Synthesis:

The logical synthesis is taken care to describe to the passage from one behavioural description to logical level to one structural description, always to logical level.

 

2) combinatori and sequenziali Circuits:

For the combinatori circuits the escape is function only of the income while for the sequenziali circuits, the escape attualeè function of the incomes and the previous state.

 

3) System optimized on two levels of logic:

It can be implemented by means of a Or di And or by means of a And di Or, in both the cases the first level of logic has a number of incomes so elevated for every door to render impraticabile such optimization.

 

4) Transform the function in one sum of mintermini:

 

5) Representation of the mintermini for a circuit more exited:

Two columns are had, in one an express configuration of incomes in terms of 0 and 1 appears the mintermine directly that is while in the other the escapes appear, di.le which if it considers some to only 1 one to the time.

 

6) K Map:

It is adapted to the minimizzazione of functions until 4 incomes, their possible combinations of income are represented coded Gray so that adjacent configurations only differ for a bit.

 

7) logical Configurations in order to represent one sum of products:

Pu² to use or a And di Or or to take advantage of the rules of De Morgan and to use a Nand di Nand, such solution is best in how much the And door is simplest to realize and fastest, moreover it is always better to use all doors of the same type so as to to optimize the area.

 

8) Implying and its representation :

Implying is with of mintermini in which some incomes instead that to be it determines you to 1 or 0 can be of the X, Don' t Beloveds.

 

9) Cover and typology :

A cover is a group of implying such to cover all the mintermini. The minimal cover contains the minimal number of implying such to cover all with, the cover is instead irridondante if some implying are contained to the inside of others.

 

10) Implying first and implying essential:

Implying is first if entire it is not contained in an implying other, it is then also essential if implying other contains at least a mintermine not contained in some, therefore must necessarily be comprised in the minimal cover.

 

11) exact Minimizzazione to two levels:

The following algorithm is used:

to)       the mintermini are identified

b)       the mintermini are attempted that they have little

 

12) Minimizzazione heuristic to two levels:

The exact minimizzazione often can carry to a number much high one of mintermini, with the minimizzazione heuristic is attempted to avoid to calculate them all preventively, they are used therefore of the rules that concur to characterize of mintermini beginning from a group begin them and subsequently they come eliminates the mintermini to you comprised.

 

13) Expansion:

Part from a mintermine and test to expand in all the directions being taken advantage of of the heuristic rules, naturally are valid the arrival configurations for which implying constituted from an equal number is had of mintermini.

 

14) Reduction:

Part from a brace of implying itself that they are overlapped and tries of implying ridursi to that they are not overlapped.

 

15) Change of shape:

Implying can be transformed in implying having an other shape.

 

16) logical Optimization of combinatori circuits multilevel:

The combinatori circuits multilevel are more use you even though they are enough difficult to synthetize, are based on a graph in which there are of you concern us for the incomes, of you concern us for the escape and others you concern us that they contain of the functions that concur to pass from the income to the escape. Following of optimization of the graph are previewed technical:

to)       Elimination

b)       Decomposition

c)       Simplification

d)       Extraction

and)       Substitution

 

17) Methods of optimization:

Pu² to optimize itself it is the area that the performances

 

18) Condition of testabilità:

A circuit is testabile on condition that not there are irridondanti covers in its K map.

 

19) ATPG:

Automatic Test Pattern Generator, draft of an instrument that resolves to do to characterize with of carriers of income in a position to testing the circuit completely.

 

20) Machine of Mealy and Moore:

A machine of Mealy is a machine to states for which the escape is function only of the states while the machine of Moore is a machine to states for which the escape is function is of the state that of the incomes.

 

21) Diagram to states:

In a diagram to states, you concern to us represent the states, arches to it they represent the transitions from one be to an other and are hung to you with two stringhe of bit, one characterizes the configuration of the incomes and the other the configuration of the escapes.

 

22) Optimization of a sequenziale system:

The optimization is articulated in three is made:

to)       location of the n° minimal of states, it is carried out characterizing the intersection between with of the states that have the same income and the same escape and with of the states that have the same income and the same final state. Between the other states then those are prechosen that concur to obtain the cover.

b)       one is associated binary word to every state

c)       ignites the machine