Planning and realization of ASIC
1) Law of Moore:
The law of Moore evidences a constant evolution of integration of transistor in the integrated circuits, in particular is had that the number of present transistors in a processore doubles every 18 months, such result has had is to improvements in the fabrication processes that in the software of automatic planning.
2) Cost of a system:
The cost of a system is given from 
the
where:
CR is the recurrent costs like those relati to you to the materials being necessary to the fabrication
CNR is the not recurrent costs relati you as an example to the planning
CF which are the fixed costs those for the publicity and the handbook
N is the produced and sold pieces number
3) ASIC:
Application Specific Integrated Circuit is a integrated circuit face to acquit in a circuit a particular function that it is not in kind implemented from other integrated circuits in commercio.Vi are various typology of ASIC that distinguish between they for complexity and costs, in particular has the technology long,…complex, expensive and ottimizzatrice Full-Custom () and Semi-Custom that in its turn are subdivided in the categories Cell-Based (Standard-Cell and Cell-Generators) and Array-Based (Prediffuse or Precablate).
4) Full-Custom Planning:
They choose this planning when standards must be realized of the cells to insert in more complex blocks or in order to realize analogic circuits. It is made of the planning are following:
to) based on the detailed lists a technology is chosen and the correspondent foundry that supplies the designs rules.
b) By means of a software Schematic Entry immette the schematic one specifying also the physical parameters of the active members.
c) the circuit immesso comes simulated using the models supplied from the foundry.
d) by means of a Layout Editor they come specified geometries of every layer of the integrated circuit, in the program is present also a Design Rules Checker that verification the respect of the designs rules.
and) a software of Parameter Extraction supplies the schematic correspondent to the layout inserted, in such a way can be verified the operation of the real circuit in which they will be senz' other present some elements you adorned to you.
f) the plan comes saved in a format standard CIF or GDS2 and envoy to the foundry.
5) Rules Design:
Draft of suggestions supplied from the foundry to the planner full-custom to the aim to maximize the probability that the circuit functions correctly, in particular the detailed lists regard ties electrical workers (…faces to avoid breakdowns to character electrical worker) and realized (faces…to you to avoid geometric breakdowns).
6) Characterization of one digital cell them:
A digital cell totally is characterized them from the following largenesses:
to) logical function
b) ability in pF on the pin to income
c) time of delay for every transition in escape, it is made up of a time of intrinsic delay and a time of delay which had to the ability seen in escape and measure in ns/pF
7) geometric Characteristics of one Standard-Cell:
Standard-Cell is characterized from constant height and variable width, to the inside of one whichever cell
n-well and the metalizations of the feedings are always found to the same height so as to to be able to place side by side two cells without preoccuparsi of these logons, moreover up and low they are present in metal-1 marks them of income and escape to the cell, such logons come carried out by means of of metalizations with at least 2 metals, in kind
metal-1 it realizes of the vertical lines and
metal-2 the horizontal lines, laddove there is need of a logon, a hole
in oxide is often made that it separates the two metals and one is
come true VIA.
8) Standard load:
E' the medium ability to income of a door, is used in order to characterize the ability on the pin of income of one
Standard-Cell, follows some that also the times of delay are expressed in ns/SL.
9) Planning Semi-custom Standard-Cell:
The plan is articulated in following is made:
to) based on the plan detailed lists the technology is chosen that is foundry and bookcase.
b) with the Schematic Entry the requests of the cells rendered available from the foundry are placed in the outline electrical worker
c) is carried out a digital simulation them of the circuit, it holds account is of the aspect works them of the circuit that of the times of delay which only can but be estimates in how much a part to you of the time of delay depends on the escape ability which in its turn depends on the abilities of income of the doors following but also from the length of the logons which is famous only after the Placement & Routing.
d) from the schematic one by means of a software of Placement & Routing the layout is obtained of the chip, in particular it comes before tried the disposition of the cells that diminishes the length of the connections in how much in such a way diminishes also the ability parasite and therefore the times of delay and the dissipated power. The function cost to optimize prechoice is not in kind the sum of the lengths of the connections, must in fact also hold account of the average and the variance of the distribution of the lengths. Once chosen the function cost and realized the optimization, is proceeded to the Ruotine.
It is possible also to change to technology to completed plan on condition that the foundry supplies the conversion parameters, in any case in fact the customer is unaware of of the layout of Standard-Cell.
10) Planning seeds-custom with Cell-Generators:
Draft of macrocells that realize functions beginning from implementabili standards in way automatic rifle a description to high level, is this the case of circuits which memories, co/decodificatori and combinatoria logic. The generated macrocell the software must then be inserted in the chip on which then the software of Placement & Routing will have to act.
11) Planning Array-Based seeds-custom:
The Array-based planning is proposed to reduce the times of realization of the ASIC and the planning costs, in order to obtain this result, the base of a integrated circuit is come true generic, which it comes then personalized from the planner, the two following approaches are distinguished in particular:
to) MPGA it is a prediffuse Array containing transistors, logical memories, doors, generic elements lacking in the metalizations which come characterized from the planner on the base of the application, in this way the time of fabrication in foundry is reduced from the 4 months of the Standard-Cell planning to 2 weeks.
b) FPGA in this case the Array contains is the programmabili logical blocks (…by means of which the sequenziali functions can be realized also) that the logons (…which can be realized by means of of the logon matrices), in particular the logon can permanent (…by means of be dispositi you as the melted ones that it introduces a high if not programmed and low resistance if programmed) or programmed to the action of the given initialization of the device reading from an external memory, in this last case the configuration is more expensive but flexible.