Theory of transistor MOS

1) Typology of transistor MOS:

There are the transistors nMOS and pMOS it is of the type enhancement (…for which it is necessary to apply a tension of opportune sign to the gate ones to the aim to form the channel) that depletion (…for which the channel is formed also for V_GS = 0).

 

2) Principle of operation nMOS:

A substrate is had p-doped in which they are gains two equal traps to you n-doped, one for source and the other for the drain, they are separate you from a space over to which there is the oxide and the gate ones, for V_DS = 0 the following situations are had:

to) Accumulation: applying a negative tension to the gate ones regarding the substrate, the present gaps in it will be recalled towards oxide therefore in pressed its will be had accumulate of gaps and therefore current in how much does not slide has two splices pn in contropunta.

b) Svuotamento : applying a positive but inferior tension to the tension of threshold V_T is had that the gaps come removed give to oxide close therefore create one emptied region of bearers

c) Inversione : applying a advanced positive tension to V_{the T} is had that they come recalls electrons to you from the substrate that therefore come to constitute a channel that puts in contact source and drain.

In case V_DS ¹ 0 it is necessary to hold account is of V_DS that of V_GS in order in particular to establish the region of operation of the nMOS if V_GS < V_T is in interdiction in how much the channel is not formed from the side of the drain while for V_GD< V_T it is in saturation and the channel is not only formed in the pressed ones of the drain. In intermediate situations, the channel is formed and it is in region of triodo or not-saturation.

 

3) Tension of threshold V_T :

The tension of threshold V_T is due to the fact that is necessary a positive tension leggermente in order to remove the majority bearers and to recall the minority ones, it is worth where is the tension of threshold for a not present MOS that difference of function job between gate and substrate being upgrades them of the bulk and loads with the bulk while is the tension of flat band with Q_fc loads due to the superficial states. Alla light delle previous chosen relations is obvious that a time the materials for the gate ones and for the substrate, V_t it can have varied acting on N_To , Q_fc (…by means of impiantazione of Ionian) and C_ox (…using different materials insulators for the gate ones).

 

4) Model base of the nMOS:

to) interdiction : _{the DS} = 0 for V_GS < V_t

b) not saturazione: per 0 < V_DS < V_GS - V_t

c) saturazione : per 0 < V_GS - V_t < V_DS

being the gain factor.

 

5) regarding Effects of 2° the order the NMOS:

to)       Body effect

The substrate of the nMOS normally is connected to V_SS , that determines V_{a SB} = 0 however in some logical structures as that one of the Nand can be necessary to place in cascade of the nMOS and therefore for some of they necessarily _SB ¹0 will be had V. The effect of this tension is to increase the threshold tension, in fact this V_SB is behaved as an inverse polarization and therefore neutralizes the free charges and increases to the extension della region of depletion, of it derives that in order to form the gate channel it is necessary to more apply al one elevated tension. In particular the expression of the V_t that it holds account of V_{the SB} is comprised with g between 0.4 and 1.2 .

b)       Operation sottosoglia

For V_GS < V_t it is in interdiction however_{the DS} also being much small it is not null and it has a exponential course that can be used for systems to low consumption.

c)       Modulation of the length of the channel

In saturation the channel completely is not formed but of it small extension from the side of the drain lacks one, that determines a lessening of L and consequently an increase is of relationship W/L that of b , therefore an expression of_{the DS} that it holds account of this effect is comprised with l between 0.02V^-1 and 0.005V^-1 .

d)       Variation of mobility

Mobility diminishes with the drogaggio and with the increase of the temperature, moreover mobility of electrons is double regarding mobility of gaps.

and)       Effect Tunnel

In the case that the oxide of gate is a lot until you can be passage of current from the gate ones is towards the source that towards drain for effect the Tunnel second the equation .

f)        Punchthrough

If the tension applied to the drain is much elevating, it can be had that the emptying region extends until to the source, and therefore can slide one independently current from the tension of gate.

g)       warm Electrons

When the length del gate is much small and the transistor is in saturation has an elevated electric field dal side del drain, this gives to place to electrons many energetic sayings warm electrons which goes to impattare with present gaps nel drain and they push to them towards the substrate or in some cases towards the gate ones giving therefore place to delle currents.

 

6) Model of the nMOS for small marks them:

In this model the abilities between the various clips are present all, an escape conductance is obtained supposing that the MOS works in not-saturation region and therefore deriving regarding V_DS the it is obtained

While for transconduttanza g_m it is necessary to derive I_DS regarding V_GS .

 

 

7) Diode valve:

It is a splice pn for which the expression of the current is therefore in the case of inverse polarization has only the inverse running weak person_s the due to the minority bearers while in the case of direct polarization a exponential course of the current in function of tension V has itself applied to i heads of the diode valve.

8) BJT:

It is a sandwich npn or pnp for which the following model is had:

to) Interdizione : both the splices are polarized inversely, of it it derives that it does not slide current between emettitore and collector.

b) Attiva : the splice base-emettitore is directly polarized therefore its heads is had approximately 0,7V while the splice base-collector is polarized inversely, in this case_{the C} = b_{the B} .

c) Saturazione : both the splices are polarized directly, it is had that to the heads of the splice base-emettitore there are approximately 0,7V while between collector and emettitore there are 0,2V.

A model that very represents the operation of the BJT is the model of following Ebers-Moll:

For which it is reached quickly the expression where V_To it is the tension of Early due to the reduction of the length of the base and is worth approximately 50V.

 

 

 

 

9) Inverter nMOS with saturated cargo nMOS to emptying:

A nMOS is had having as loaded a nMOS depletion which it comes made to constantly work in saturation simply cortocircuitando the gate ones with the following escape according to outline:

for famous it that , in order to determine the tension of income for which the commutation from high to bottom is had, is necessary to suppose both the MOS in saturation and uguagliare the currents, is obtained where . Evidently being for pull-down the for having the running principle it is necessary to reduce V_tpd but it cannot be reduced too much otherwise cannot be had V_out inferior to it and to extinguish the MOS, in kind chooses V_tpd = 0.2V_DD , analogous for the pull-up is had therefore is necessary to increase V_tpu for having the running principle but that implies to increase the relationship with consequent increase of the occupied area therefore imposing the equality of the currents between pull-up and pull-down V _tpuis obtained = 0.8V_DD but in kind is reduced to us to 0.6V_DD that it implies that if _INV is desiredV = 0.5V_DD is necessary to have .

as one looks at the characteristic is that one of a inverter that it carries out the maximum excursion and that slope has one much elevating or in order better to say a gain elevated in correspondence of the high passage downstairs.

 

 

 

 

 

 

 

 

 

10) Inverter pseudo-nMOS:

Draft of a inverter in which the pull-up it is constituted from a pMOS that it is behaved like a nMOS

11) Inverter CMOS:

It is a inverter with optimal performances in how much guarantees the complete excursion of V_{the DD} and one of the two MOS does not dissipate power in the stable states in how much is always interdetto therefore not is never one logon directed between V_DD and V_SS . The analysis is carried out subdividing the study in 5 regions of operation that determine considering that the MOS can be found in interdiction, linear region or saturation. We consider one V_in crescent from V_SS to V_DD :

0 < V_in < V_tn : the nMOS is interdetto therefore the current that crosses it is null as pure therefore the current must is null that crosses the pMOS which instead it is in active region therefore V_DS = 0 and V_OUT = V_DD .

V_tn < V_in < V_DD/2 : the nMOS enters in saturation while the pMOS it is in linear region, uguagliando the two expressions of_{the DS} previa substitution of V_GSp = V_in â?"V_DD e V_DSp = V_out â" V_DD obtains the expression of V_out .

V_in = V_DD/2 : both the MOS are in saturation, draft of one be unstable valid only for this value of the income tension, the value of the escape tension are not determined univocamente.

V_DD/2 < V_in < V_DD V_tp : the nMOS is in linear region while the pMOS it is in saturation, uguagliando the two currents obtains the expression of the V_out .

V_in > V_DD - V_tp : the nMOS is in linear region while the pMOS it is interdetto, ci² determines that V_out = V_SS

It is from observing that we have placed V arbitrarily_inv = V_DD/2 while its expression is gained imposing the saturation for both the MOS, has from which evince that to growing of the relationship of i b the V_inv it diminishes while the ripidità of the curve remains unchanged, however is chosen advised to have the b equal, in such a way in fact loads and the discharge of the cargo ability is temporarily equivalents.

 

12) Margins of noise:

We consider inverter a CMOS that pilot a second inverter CMOS, the escapes of the 1° advanced to V_OL comes considers low levels you while those advanced ones to V_OH come considered high levels. For the 2° inverter instead, the inferior incomes to V they come considers low levels you while those advanced ones to V_IH come consider high levels you, naturally in order to avoid of having a indeterminata zone convene that V_IH = V , values that can be determines you from the characteristic curve characterizing the having points slope â?"1 (…than then corresponds to the gain being the curve that expresses Vaccording to _out V_in). They come defined the noise margins that say how much to us can be elevated the noise in order not to recognize a level like an other, have e

 

13) Inverter BiCMOS:

It is a inverter particularly adapted laddove must be piloted great cargos to high speed, such performances in fact can be only obtained with one exited BJT, the outline is following:

for V_in = 0 P ₁is had on that therefore it after all sends in conductionNPN _{the 1} whileNPN ₂ is interdetto fromN ₃, escape door to V_DD â " V_BE . For Vin = 1 N ₁is had on and therefore NPN₁ is interdetto while N₂ sends in ₂ conductionNPN and therefore the escape door to the value V_CEsat that is to approximately 0,2V, therefore the excursion of this inverter is not maximum and creates problems in the case of many inverter in cascade.

 

 

14) Transmission Gate:

E' a device a lot used in order to realize multiplexer and exited tristate, the study of its operation comes carried out separately for the nMOS and for the pMOS supposing that there is an ability connected to the escape, it is had:

If S=0 the nMOS is blocked independently from the value of the income while for S=1 if V_in= the 1 condenser it is loaded and being V_GD = 0 it is in saturation, but _DD loads does not arrive until toV _DD in how much the nMOS passes in interdiction forV _out =V- V_t Quando V_in pass to 0 the condenser must be unloaded, the source more negative of the nMOS is the clip and therefore that one of income therefore V_GS initially is equal to V_DD > V_t therefore the channel is formed from the side of the source and it it is also from the side of the drain in how much has V_GD > V_t , it is therefore in region of triodo and the condenser discharge completely in how much from the expression of_{the DS} is had that it only cancels itself if V_DS = 0. From the previous ones it is deduced that the nMOS he is ideal in order to concur the passage of the low levels, but insufficient for the high levels.

If - S=1 the pMOS is blocked independently from the value of the income while for â?"S=0 if V_in= the 1 condenser are loaded, in this case V_SG > V_T and therefore the pMOS it is always in conduction and the condenser loads until to V_DD . When V_in = 0 the condenser must be unloaded but when it reaches value V_t , interdice therefore it is achieved some that the pMOS it is behaved well in the transfer of the high levels and badly in the transfer of the low levels.

After all the transmission gate if S=0 has an escape in high stiffness that leaves the condenser its value of it loads while if S=1 the high levels come it passes to you in escape from the pMOS while the low levels come pass to you from the nMOS.