Methods for the test of the CMOS
1) Typology of test:
The test of a chip can happen to level of wafer, chip, sideburn and of system however before it comes characterized out of order, smaller the die is the loss of moneies deriving from that breakdown. The tests can be divided in two great categories, the Functionality test and the Manufacturing test.
2) Functionality test:
It is a test face to verify that chip in its the entirety implements the function effectively for which has been developed, in order to carry out such verification would be necessary to apply to all the possible combinations of incomes but in order to make that in the case of systems many complexes could be necessary of the years, then is made I use of the hierarchy inherent to the system in order to verify the modules singularly
3) Manufacturing test:
It is a test face to verify that every door present in chip the works like previewed, becomes in how much the process of fabrication of the chip necessary can give place to defects like following:
to) short circuits between various layers of metal
b) broken off logons
c) oxide of gate in short towards the substrate or the well
The tests come are executed to level of wafer and verify also the levels of the escapes and the incomes, the speed and the absorption.
4) Models of breakdown:
The defects that can be introduced in the course of the production are short circuits and opened circuits, they come call failure to you while their modellizzazione comes called fault, between the possible ones fault are had:
to) Stuck-at-0
b) Stuck-at-1
c) Stuck-open
d) Stuck-shorted
Draft of all breakdowns that must be modellizzati to level of MOS.
One of the typical effects of this type of breakdowns on circuits CMOS is that they can make to become sequenziale a combinatorio circuit.
5) Osservabilità , controllability and cover:
A osservabilità of an inner node to the circuit is the degree with which it is succeeded to observe from the escape its state, while the controllability is one measure of the ability to settare a node to 0 or to 1. The cover of the breakdowns is instead a measure of the quality of a test program, in fact for a data number of carriers it applies to you is settled down that percentage of the inner nodes comes head, such percentage is obtained sequenzialmente placing every inner node to the circuit before to 0 and then to 1, and the escapes come compared with those of a chip not settato, if there are discrepancies has a fault, the percentage of the fault find to you regarding those simulate to you express the cover of the breakdowns.
6) ATPG:
Draft of methods that generate the carriers of test (Automatic…automatically Test Pattern Generator), all is based on a simulation of the circuit which it can in every node assume from 5 to 10 various states to second of the ATPG, considering some one to 5 states they are:
to) 0
b) 1
c) X Don' t Beloveds
d) D is worth 1 for one working machine and 0 for one out of order machine
and) 
is the denied one of D therefore is worth 0 for one machine working
and 1 for one out of order machine
In order to see as they come it generates you the test carriers we make reference the circuit
We suppose of having to characterize a S-A-0 to the node h that therefore it will have D value, pursue the two objects to you intermediate:
to) settare the node h to the D value by means of a set of primary incomes
siccome we want to characterize a S-A-0 evidently the machine works correctly if we succeed to place h to 1, to such aim reasoning with the tables of truth of the logical doors looks at that the incomes {to, b, c, d} also can be {1,1,1,0} op {1.1.0.1}
b) propagare D from the node h to one of the primary escapes which are directly observable
so that it can be verified that h it is to 1 it is necessary that and it is the 1 after all therefore carrier of the incomes must be {1.1.1.0.1} or {1.1.0.1.1}
In analogous way they obtain of the income carriers that the S-A-1 for the same node verifies after which the other nodes are estimated of the carriers for all, once found this entirety much large one, is attempted to find the minimum with of the income carriers that cover all the nodes.
It is observed that the state can be
useful in the cases in which a data node turns out inosservabile.
7) Classification of the breakdowns and simulation:
The node to test comes place to 0 before and then to 1, they come applies you you respect test carriers to you and the escapes primarie confronted with those produced from the circuit in which no node has been arbitrarily place to 1 or to 0.
If there are of the discrepancies the breakdown has been characterized and it is passed to the next node. The process therefore demands S K= KN totally cycles of clock where K is the number of nodes to put out of order and N is the medium number of test carriers, such number of cycles can become very high therefore can be rerun to a simulation parallel or to the concurrent simulation.
8) Strategies of planning oriented to the test:
The plan oriented to the test is based on one of the following approaches:
to) Testing to-Hoc
Draft of strategies times to reduce the combinatoria outbreak of the testing, between these is:
a1) to partizionare the sequenziali circuits of dimensions elevated to example a contatore to 8 bit that demands 256 carriers of test can be subdivided in 2 4 contatori to bit every goddesses which demands alone 16 carriers of income in order is tested.
a2) to add test points
a3) to add multiplexer which concur precaricare of the incomes
a4) to easily concur to pass to the state of reset
b) Testing based on the scansion
It is necessary that the 2 following conditions are verified:
b1) the circuit must be sensitive to the level that is the
stationary answer to variation of the incomes does not depend any on
inner delays to the system from the order in which the incomes have
varied be.
b2) every registry can be converted in one shift-register seriale
The block base is the SRL (…Shift Register Latch) which it can be realized by means of two latch
D is its income and 2T its escape, such SRL can is placed in cascade second the outline
In such a way one obtains that every income is controlable and every escape is observable.
c) Self Test
In the chip they come added of the having circuits the scope to execute the test of the circuit
c1) Signature Test
E' a test based on I use of a generator of sequence pseudorandomico
, in the fattispecie they come applies the test carriers to you and the escapes of the circuit are gone to add to the content of a LFSR (…To delineate Feedback Shift Register) which to the end syndrome will contain a said number that it can in such a way be compared with the correct syndrome determining if the circuit works correctly or less.
c2) BILBO
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Draft of the union of the Signature Analysis with the techniques of scansion in particular on the base of 2 incomes can be decided the operating modality of a group of registries.