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Methods of planning CMOS

1) progettuale Description of a integrated circuit:

A integrated circuit can be described in the behavioural, structural dominion and physical, everyone of these dominions can then be subdivided in the levels:

to)       architetturale or they works

b)       RTL (Register Logic Transfer)

c)       Logical

d)       Circuita them

 

 

 

 

 

 

2) Strategies of plan:

Scope of the planner is to realize a plan that optimizes the performances, the dimensions, the necessary time to the planning and the testabilità, to such aim becomes necessary to resort to the structured planning which, in analogy to how much happens for the software, stretches to realize plans characterizes to you from the following property:

to)       Hierarchy

Every module comes ricorsivamente subdivided in sottomoduli having inferior complexity and therefore until obtaining of the easy implementabili modules. In such a way it is moreover possible to subdivide the planning between various work groups.

b)       Regolarità

The hierarchy can give place to n° much elevating of sottomoduli, the complexity reduces a lot if these are almost equal, so as to to be able to re-use the same module rather than to realize of many all between various they.

c)       Modularity

One consists in implementing very specifies interface with the outside.

d)       locality

draft to be attempted to complete all the elaborations to the inside of the module and to try to reduce lessened marks them that they must be interfacciati with the other modules.

 

3) progettuali Options CMOS:

Proceeding in order of investments for the planning increasing, the following progettuali options are had:

to)       Logical programmabile

b)       Sea-of-gates and Gate Array

c)       Cell Standard

d)       Full-custom


4) Logical programmabili:

The logical programmabili stretch to produce of chip the many complexes but it adapts to various applications so as to to be able some to produce to a number much high one reducing therefore the costs, the planner moreover is benefitted in how much the planning and realization happens in short times much. The following typology are had

to)       programmabili logical structures

Draft of the PAL and the PLD that in short are characterized from a flat And and a flat OR which puttinges in communication by means of of the connections are come that can be realize to you going to act on the characteristics of a following element of commutation with one of technologies:

a1) Fuses

All the logons are realized, in phase of programming in order to obtain the wished function come made to pass one current much high one in the logons that do not interest, in such a way obtain the opening of the connection

a2) EPROM

The gate ones are based on the floating gate that is a metal place to the inside of below oxide effective, for the programming the gate ones come fed to 14V while the drain to 12V, in such a way iniettano of the gate charges in the floating and therefore the tension of threshold V t to the disopra is raised of the feeding tension, and therefore the MOS in gate issue remains interdetto sin when it loads present in the floating does not come expelled by means of exposure to beams UV.

a3) EEPROM

Always they are based on the floating gate however in this case is possible to cancel the interconnections and riprogrammar them by means of effect Tunnel, to such aim the floating gate is realized so as to to be much neighbor it is to the gate ones that to the drain.

b)       programmabili interconnections

Draft of structures based on the PLICE (…Programmable Low Impedance Circuit Element), a device which normally it introduces a greater resistance of 100MW but that by means of opportune tensions of programming W can be settato permanently to a value of resistance of approximately200 . The chip it is constituted from lines of logical elements separated from lines of horizontal interconnections and vertical fixed, the interconnections between these come carried out by means of the programmed melted ones opportunely by means of of pass the transistors. Every logical element Actel as an example contains 3 Mux to 2 incomes and a NOR to two incomes and can implement all the functions to two and three incomes and some functions to 4 incomes. To the periphery of the chip they are present then of pad the I/O that always by means of PLICE can be programmed as pad of income, of escape or bidirectional.

c)       gate arrays riprogrammabili

The structure is much similar one to that programmabile but in this case the interconnections can riprogrammate to such aim around to the CLB (…Configurable Logic Block) have horizontal and vertical lines of interconnections, personalized by means of commutation matrices, which the CLB is connected by means of of the PIP (…Programmable Interconnect Point). It is the PIP that the matrices are shaped by means of of the pass-transistors piloted from memory RAM.

 

5) Plan of Sea-of-Gate and gate arrays:

Small can be realized productions by means of structures Sea-of-Gates or Gate Array, of the structures that the foundry supplies realized until to the level of the polisilicio, remain therefore from 2 to 5 masks that they must be realized from the planner in function of the applicativo, achieve some that the times of planning and realization are many bottoms also in function of the reduced demanded procedures of testing.

The structure of a SOG is constituted from lines in which is present a spread line p and a gate line of spread n spaced out from in polisilicio, up and low is the metals assigns you to the feedings. All around to the chip there are cells I/O that can be programmed by means of metalizations. The logons happen over the MOS do not use you while in gate the Array there are of I affixed horizontal channels to you.

E' important to remember that the MOS finish them of a door is uses you in order to isolate from the adjacent doors connecting the gate ones of nMOS to VSS or the gate ones of the pMOS to VDD .

 

 

 

 

 

6) Plan of Cell Standard:

The Cell Standards consist in of the bookcases that carry out a standardization to logical level, therefore are implemented various logical structures of common use, in kind then every logical function come realized in two various cells, one that optimizes the area and one that the speed optimizes so as to to answer to all possible requirement.

Regarding gate the Array many more masks must be realized, approximately 15, but it is obtained more rations I use them of the resources in how much the plan is more adherent to the specific application.


7) Full Plan custom:

It is a planning that optimizes the function and the layout of every single MOS, is much complex, as well as to be reduced to circuits with less than 100 MOS and demands planners many experts, however for some applications in which they must be optimized determined specific, is the better solution even if the costs are a lot elevate to you as also the times of planning and realization in how much are necessary all the masks.

The realization of the masks happens technical following second:

to)       symbolic Layout on crude grill

In short the area of the chip comes subdivided by means of a grill with cells of equal dimensions to the minimal obtainable resolution, every cell contains a symbol that identifies the combination of layers that must be present in one given cell.

b)       symbolic Layout to matrix of gate

E' characterized from a layout to regulate, in particular is of the horizontal lines of spreads n and p and of the vertical columns of polisilicio, to every intersection potentially you pu² to be a MOS. The rules standard are following:

1)       the polisilicio slides alone in a direction and is of constant amplitude

2)       the spreads slide vertically between the polisilicio columns

3)       the metalizations can slide are vertically that horizontally

4)       the MOS can only exist to the polisilicio columns

c)       symbolic Layout to virtual grill

A virtual grill is had on which the elements are arranged of the circuit, in such a way they come eliminated the designs-rules and comes defined coordinodo that is a node that beyond to geometric property possesses also the typical property of a node in a circuit that is tension, current, state.

 

8) progettuali Methodologies:

to) Synthesis they works

They are used of the Silicon-compiler like Cathedral which give a description of the plan to level work them arrive until to the masks, in particular they come executed the following operations:

a1) it comes decided the allocation of the resources on the base of the detailed lists on the area and the temporizzazioni

a2) they come inserted of the registries pipeline in order to respect the temporizzazioni

a3) it comes created the code and logic of control

b) Synthesis RTL

Programs like VERILOG and VHDL which leave from description RTL and are used convert it in a set of registries and combinatoria logic. The information that must be supplied to the program are:

b1) flow of control implemented through if-then-else or houses

b2) iterances

b3) hierarchy

b4) lengths of words, carriers and matrices of bit

b5) Specific on the registries and allocations

b6) arithmetical, logical Operations and of comparazione

 

9) Instruments for the capture of the plan:

The operation and/or the structure of a plan can be implemented by means of languages HDL, alternatively and more classically the schematic one can be inserted. Analogous the layout it can be implemented by means of of a code or by means of a editor, moreover programs exist that work on the layout with the aim to diminish the area and to maximize the speed.

 

10) Instruments for the verification of the plan:

to)       Simulators

Most famous is SPICE, based on the solution of matriciali equations that describe the circuit, is much precise but slow one, therefore it is adapted only to the simulation of small circuits, for great circuits is rerun to the Sangiovanni-Vincentelli which making of the approximations it succeeds to analyze the circuit with simple calculations not matriciali.. There are then of the simulators that only work to logical level and simulators to level switch that they deal the MOS like open switches or sluices, finally are of the mixed simulators that execute a various simulation to second of the type of circuit that they are analyzing.

b)       Controllers of the temporizzazioni

Draft of programs you turn yourself to characterize the critical distances us

c)       Extracting machines of layout

They are programs that have in income the masks that describe a layout and go back to the circuit that has generated them, adding but eventual dispositi to you you adorned to you, the obtained effective circuit therefore comes newly therefore simulated and if it turns out to you they remain in the detailed lists is proceeded to the production. This process is said back-annotation.