Logical doors

TTL

1) Describe circuit TTL:

A transistor of income T ₁ of the type to multiemettitore is had, on the n emettitori is applies you marks them of income while on the base the feeding through the R resistance is applied_b1 , the collector is connected to the base of the transistor T₄ that acts as from sfasatore therefore on its emettitore has a resistance R_E4 towards mass while on the collector one is had resistance R_C4 towards the feeding. The two mark them in phase opposition go to feeding the BJT of pull-down ₃T and the block of pull-up constituted from T₂ (…fed through the resistance R_C2 ) and from the D diode valve.

The door in issue carries out the Nand function in how much when all the incomes are to the state high T₁ work in inverse active region and therefore it sends in saturation is T₄ that ₃T and therefore the escape is to the low state while if also one of the incomes only is to the low state it has that interdiceT ₃ and T₂ is in active region and therefore the escape is high.

 

2) Behavior of door TTL in the case of income to the low state:

J_BE1 is polarized therefore T ₁directly can be found or in active region or saturation, in order to verify its state it is assumed that it is in active region and currency therefore_{the C1} = b_{the B1} , finds that current of the order is one of but that it would have it are supplied from the base of T₄ derives some that ₄T interdice and therefore0 _C1 @ therefore T₁ is in saturation, in such interdice way ₄T and consequently T₃ while it is T₂ that the D diode valve is in the active zone and therefore analyzing this mesh it obtains that the escape tension is worth 3,6V.

 

3) Behavior of door TTL in the case of income to the high state:

J_BE1 is polarized inversely while J_BC is polarized therefore T ₁directly finds in inverse active region, while ₃T and T₄ can be in active zone or saturation, that it involves that on the base of T₄ us it can be a tension comprised between 1,4V and 1,6V _{the B1} can therefore be estimated and multiplying it for b @ the 0,02 to obtain that the base current goes to end nearly completely in the collector of T₁ . We assume that it is T₄ that T₃ is in saturation that it implies to have V_{a CE4} @ 0,2V and V_{a BE3} @ 0,8V with these values we calculate_{the C4} and being already famous b_{the D} and_{the B4} I can calculate s and to verify that effectively T₄ is in saturation, clearly being also T₃ in saturation is had that tension V_out = V_CE3 = 0,2V.

 

4) Behavior of door TTL in the passage from low level in income to high level:

If V_in are to the low state it has that T₁ is in saturation therefore V_CE1@0,1V, of the rest has V_B4 = V_in V_CE1 therefore to growing of V_in grows also V_B4 and when this catches up the value 0,65V (…which V _in=correspond 0,55V) are had that T₄ begins to lead but for via of the fall on J_BE4 it is had that T₃ will remain interdetto sin when V_in= 1,35V beyond which the escape tension diminishes very fastly until catching up the value of 0,2V.

 

5) Margins of noise of door TTL:

in fact beyond 0,55V in income the escape is had gradually passes from the high state to the low state while for tensions of greater escape of 0,2V T₃ it is not more in saturation.

Moreover is had.

 

6) Fan Out of door TTL for high level in escape:

If the escape is to high the logical level the T₁ of the N connected doors they work in inverse active region, and therefore their cargo transistors T₃ and T₄ are in saturation that it involves one tension V_B4= 0,75V 0,75V=1,5V moreover being directlypolarized J _BC1 will be had that the tension V_B1= 0,7V 1,5V=2,2V, can therefore be calculated_{the B1} and multiplying it for b obtaining the current absorbed from every door that is indeed insignificant that is approximately 14mTo, multiplying it for the number of the doors the current is gained_{the E2} that slide in the emettitore of the door driver and dividendola for (1 b_D) obtains the value of_{the B2} , analyzing the escape mesh is had that when_{the B2} increases the tension V_out it diminishes therefore if we want to fix we must determine the minimal value that V_out pu² to assume and therefore the maximum value of_{the B2} and therefore we obtain the maximum number of doors that can be connected, comes 2550 but in kind the constructor recommends a maximum of 10 doors.

 

7) Fan Out of door TTL for low level in escape:

If the escape is to the logical level low T₁ of the N connected doors they work in saturation, and therefore their cargo transistors ₃T and T₄ are interdetti while T₂ is found in active region. In order to calculate the current distributed from ciascuna cargo door the tension V _B1 is estimated that is the sum of 0,2V had to V_CE3 of the door driver with T₃ in saturation and 0,8V had to V_BE1 of the cargo door with T₁ also it in saturation, pu² therefore to be estimated_{the B1} that being T₄ interdetto it coincides with_{the E1} that is with the current distributed from ciascuna cargo door, multiplying it for the number of the cargo doors _{the E3} obtains the current @ _{the C3} that slides in T₃ of the door driver. To growing of the absorbed current T₃ it ends in order to exit from the saturation that it happens when s > 0,85 imposing this value a fan-out is obtained maximum of 100 doors but the constructor recommends to connect some in emergency until to 10.

 

8) Appraisal of the time of climb for one door TTL:

LžH When the escape passes to the high state has that the cargo condenser must be loaded, that _{the C2} happens with one current that is obtained multiplying for b the current_{the B2} that being T₄ interdetto (…and therefore does not absorb current) can be estimated simply. Replacing an equation is obtained differentiates them from which evince that it loads he will be naturally exponential with time constant .

HžL is had that T₃ must work in region attiva therefore_{the C3} is constant and equal to 113mA if of it deduces that the ability discharge with one constant current sin when it does not reach 0,2V.

ECL

9) Describe door ECL:

It is constituted from an amplifier differentiates them in which on the base of npn a T₂ a negative tension of reference V _R is applied = -1.175V while on the base of the other npn T₁ has the income tension, has one exited V_OR on the collector of connectedT ₁ to mass through R_C1 and one exited V_NOR on the collector of connectedT ₂ to mass through R_C2 , both the escapes then are equipped of transistor that acts as from buffer. The great advantage offered from the circuit is that T₁ and T₂ can be never found in interdiction or active region but in saturation, and therefore comes saved the time necessary riassorbire the charges from the base when it is wanted to be exited from the saturation.

In short the circuit is behaved like a current shunter that can slide all in a npn or all in the other or intermediate ways in order then to rejoin itself in the R_and . It is observed that the circuit comes fed between one negative tension and mass in order to concur the schermaggio and therefore to reduce the overlapped noise to the escape tensions.

 

10) Describe escape OR of door ECL:

We suppose that V_in are to the high state and are worth approximately 0V, is had that T₁ is in active region while T₂ is interdetto therefore the current of base of the separator T₄ is simply equal to the current that crosses the R_C2 , if for semplicità we consider it null is had that V0_B4 = therefore the tension in escape is equal to the ddp to the heads of J_BE4 that being T₄ in active region is worth 0,75V, in truth holding account of the fall on the R_C2 is had that for high income V_OR= - 0,76V.

If V_in diminish until making to pass T₂ in conduction and T₁ in interdiction it has that the escape tension is equal to the sum of V_{the B4} and of V_{the BE4} = 0,75V in how much T₄ it is in active region, of the rest V_{B4 the C2} is estimated multiplying the current=_{the E2} for the resistance R_C2 in how much is negligible and with opposite sign the base currents of T₄ and T₂ . Moreover_{and E2} can be calculated being famousV since T₂ is in active region and therefore J_BE2 = 0,75V, finds V_OR = -1,54V.

 

 

11) Describe escape NOR of door ECL:

A V_in much interdice lowland T₁ and therefore in it do not slide current therefore are had that V_NOR is the sum of V_{the BE3}= 0,75V in how much T₃ is in active region and of the fall of tension on the resistance R_C1 , _NOR is obtainedV = -0,76V that is the same tension that is had on escape V_OR when the income is to the high state.

To growing of V_in it is had that T₁ passes in active region and therefore the fall has to its heads approximately 0,3V can therefore be calculated the tension of escape like sum ofV _{the BE3} more on the resistance R_C1 which is obtained easy inasmuch as for a transistor in active region the collector current is approximately equal to the emettitore current, is obtained

V_NOR = -1,72V that V _in = are obtainedfor one -0,47V.

Increasing the V ulteriorly_in it is had that T₁ enters in saturation and therefore V_{the NOR} knows them until catching up the value of V_NOR= - 1,45V for V_in= 0V.

 

12) Determination of the amplitude of the transition region:

Both the npn in active region are considered, the emettitore currents have expression and replacing_and =_{E1 the E2} pu² to gain that just is such that when V_in= V_rif are had that_{the E1}=_{the E2} . Imposing that the relationship between the currents is worth 0,05 and also 0,95 they obtain two values of DV that they indicate as the transition region is symmetrical regarding the tension - V_Rif and is worth 150mV.

 

13) Process of commutation in one door ECL:

We consider that escape OR of a door ECL sluice on one condenser C_L passes from the high state to the state low which corresponds a tension in escape of -1,54V is had that the condenser is loaded esponenzialmente stretching to â?"5,2V but reached â?"1,54V remains constant then.

 

14) Dissipation of power in one door ECL:

We consider escape OR of a door ECL is when the income is low that when is high, the power distributed from the generator is estimated like product of the tension to the heads of the generator for the sum of the current that slides in the resistance of emettitore and of the current that slides in the emettitore of T₄ .

 

15) Fan Out of door ECL:

The Fan Out on level 0 does not come calculated in how much a level 0 in escape determines that the transistor T₁ of the cargo doors is interdetto and therefore it does not absorb current while as far as the Fan Out on level 1 the minimal level for the error margin is prevailed on level 1, as an example D1 = 0,2V and the minimal tension in escape is deduced correspondent to the high state, through it and knowing that T₁ of the cargo doors is in active zone it calculates the current absorbed from ciascuna of they. For same V_{the OH} the current distributed from the door is estimated driver and therefore it can be calculated the maximum number of doors that can be connected to door ECL, such number is approximately 500 however the constructor recommends in emergency the maximum number of 20 doors.

MOS

16) Expressions of the currents in a NMOS and a PMOS:

Region of triodo if then ha

Region of saturazione if then ha

Where being t the thickness of oxide under the gate ones, W the width of the channel and L its length.

It is observed that for a PMOS the equations are the same ones to pact to invert the pedici.

 

17) Effect of the temperature on the Mosfet:

To growing of the temperature the two effects are taken place following:

to)       V_{the T} it diminishes of 2,5mV/ °C

b)       mobility diminishes in how much the reticulum is subject to greater vibrations and therefore there are many hits of the bearers

however an increase of the temperature predominates according to effect therefore produces one lessening of the current.

 

18) Invester to MOS:

He marks them of income is applied on gate of a MOS of the type to enrichment having like cargo a resistance or in the integrated circuits an other MOS that can be saturated, or also of type to emptying so that the channel is formed already in absence of tension on the gate ones. If V_in < V_T are had that the channel is not formed from the side of the source and therefore to greater reason they do not give the side of the drain and therefore the MOS is interdetto, when V_in > V_T are had that V_DS > V_GS â?"V_T @ the 0 therefore NMOS enters in saturation, the current that slides in it is that must be replaced in the obtaining the tension of escape from the invester when it finds itself in the region of saturation from which it exits for , replacing the value of V_out previously calculated it is had that this happens for V_in = 3,4V. In the saturation region the expression of_{the DS} is , replacing it in the gains the tension of escape from the invester when the NMOS is found in the region of triodo. A parameter a lot important is in as far as growing of l_R the transition of the escape between the levels ups and downs becomes steeper and therefore faster.

 

19) Realization of doors MOS:

AND obtains placing in cascade two NMOS while the cargo is saturated that is constituted from a having MOS the gate ones cortocircuitato with the drain, is had that a tension of income V_in < V_T is considered like 0 a logical one and does not create the channel, achieves some that pu² not to slide current and therefore the escape tension is always to level 1 when to one of the two MOS of income it is applied one 0.

NOR have two MOS in parallel that is with the source and the drain in common, on this last one the MOS of cargo of saturated type is had and comes captured the escape tension that will be to the high state only when to both the MOS of income come applied 0 and therefore is interdetti and the escape is to the high state.

20) Time of climb and time of reduction of one door MOS:

The time of climb is while the time of reduction is

it is observed that the time of climb is the much greater of the time of reduction in how much channel of the cargo transistor must be along and tightened to the aim of having a fast transition between the two logical levels but in such a way small current can slide in it only one that must load the ability with the successive doors. The discharge of the condenser happens passing from the region of interdiction to the saturation region and therefore to the region of triodo, in last the two regions the times of discharge are differently estimated being various_{the DS} that slide in the MOS.

CMOS

21) Door CMOS:

It marks them of income is applied is on gate of a connected having PMOS the source to V_SS that on gate of a connected having NMOS the source to mass, the escape instead is taken on the drain of both. In short in such a way the times of commutation regarding door MOS in how much are reduced exist always a distance to low resistance for load and the discharge with the present capacitivo cargo to the escape of the door. In order to realize the symmetry it is necessary that the k of the PMOS it is approximately equal to the k of the PMOS but being mobility of electrons approximately the double quantity of that one of gaps, is necessary that the l of the PMOS it is the double quantity of the l of the NMOS.

 

22) Invester CMOS:

For V_in < V_TN he has himself that T₁ is interdetto while T₂ is in active region and therefore the escape is to the high level and is worth V_SS analogous for V_in > V_SS â?"V_TP is had that T₂ is interdetto, while T₁ is in active region therefore V­_out = 0V.

In intermediate situations he has himself that or both the MOS are in saturation or active region but having to be equal_{to the DS} , uguagliando their expressions in the NMOS and the PMOS in function of the operation region, obtains the value of the V_out for whichever tension of income. From a study of the expression of the current one finds that it comes nearly dissipated exclusively during the commutation that therefore will have to be rendered steep most possible.

 

23) Door Nand CMOS:

Part from an invester CMOS to which it comes applied one of the two marks them of income, between the NMOS and the mass places the NMOS of according to invester CMOS on whose gate the income is applied 2° which it reaches also the PMOS that is found in parallel to the PMOS of 1° the CMOS.

 

24) Door Nor CMOS:

Part from an invester CMOS to which it comes applied one of the two marks them of income, between the PMOS and V_SS places the PMOS of according to invester CMOS on whose gate the income is applied 2° which it reaches also the NMOS that is found in parallel to the NMOS of 1° the CMOS.

 

25) Dissipation of door CMOS:

The dissipated power is the sum of three contributions, a static power due to the fact that in the realization integrated is various undesired diode valves, a power short circuit that is that one that is had when it is the PMOS that the NMOS is in saturation and a dynamics power that are the dominant term and can be reduced diminishing the ability or the tension of feeding making but attention because the last provision determines an increase of the delay of the door.

 

26) Latch - Up:

In the integrated realization of door CMOS various undesired diode valves are present, they damage place to a npn and to a pnp, these two transistor are joined between they to form a circuit with with the resistances of the substrate of type n and type p. It is had that if a disturbance or a photonic irradiation increases the current on the emettitore of the npn it ingenders a positive reaction that for one small applied tension gives place to one elevated current that right ys the CMOS. In particular the curve that describes the Latch-up is characterized from a Trigger Point and one tension of Hold.

In order to reduce the malfunctioning it can or be reduced the resistances of the substrate or the gain of the BJT.