Combinatoria logic

1) Pass Transistor:

It is constituted from a NMOS which if it marks them of qualification on the gate ones it is high ago that the income on the drain is brought back on the source while if marks them on the gate ones is low, the channel is interdetto and therefore the device introduces an escape in high stiffness. The defect is that if a NMOS is used the cargo ability comes slowly loaded a lot in how much the NMOS is in saturation while the discharge happens in region of triodo therefore is much fast one, if instead a PMOS is used is had that the discharge is slow while loads is fast, these considerations is to the base of door CMOS which is proposed to take advantage of the better characteristics of the two dispositi to you.

 

2) Transmission Gate:

It is an outline constituted from a having NMOS source and drain in common with a PMOS it marks them on the Gate of the NMOS arrives invert also on the gate ones of the PMOS therefore is had that when the income is to the high state the MOS lead both while when the income is to the state low they is both interdetti and therefore the escape is in high stiffness.

 

3) Multiplexer:

Draft of a device that leaves to pass in escape a single one of the 2ⁿ lines of income on the base of the present configuration on n incomes of selection, can be realized putting a Transmission Gate in series to every line of income and qualifying of only one to the time through one opportune logic of commando.

Alternatively every line comes finished on a And door in which 2° the income comes from one logical of control and is to only 1 for one of the And, their escapes come then made to meet in one Or door.

 

4) Realization of multiplexer to N having incomes by means of of multiplexer the M<N incomes:

It is necessary to realize one falled of multiplexer so that the last one multiplexer receives like incomes the previous escapes of the multiplexer qualified from the incomes of selection added to you that they must be present.

 

5) Decoder:

It is a device that on the base of the value of the bit present on the N incomes, door to the state high only one of the 2^N exited.

Once written the truth table is observed that he is not minimizzabile and therefore the decoder can be only realized by means of one logical to two levels.

 

6) Demultiplexer:

It is a device in which one of the 2^N escape lines follows the income, the line comes selected on the base of the value of N incomes of selection. The circuit is come true in simple way by means of of the And doors in which one of the incomes he is common and equal to the income to the demultiplexer while the other income is one of the escapes of decoder having like incomes incomes of selection.

 

7) Distance of Hamming:

It is the various number of bit in a two stringhe of bit, D_H = 1 indicates that two sequences are various only for a bit.

 

8) Logic to two levels:

Two types of logical to two levels basing on 1 the present ones in the escape function exist and an other based on the 0 present ones in the same one, considering the logic based on the 1 in short that that is made is to associate every a And door to 1 the incomes of the door must be all only 1 in the case of the selected combination of income therefore if we have of the zeroes is necessary to apply a Not to such income. A number of equal And doors will be obtained to the number of 1 present in the wished function and the escapes of these And doors must all meet in an only Or door.

 

9) reflected Code or Gray code:

It is a code in which every element of codifies only differs from the previous one for a bit, code reflected in how much is called has an axis of symmetry regarding which the sequences of bit situated to the same distance from the symmetry axis differ between of they only for the first bit.

 

10) Min Term:

Draft of the sequence of bit opportunely modified with such Not doors to produce in escape from the And door a 1.

 

11) Maps of Karnaugh:

Supposing of having a system to 4 incomes, a column to ciascuna is associated of the 4 combinations of the two bit of greater weight and a line to ciascuna of the 4 combinations of the two bit of smaller weight, the combinations come inserted in the lines and columns following the reflected code in such a way is had that every combination only differs from the previous one for a bit.

The structure must be considered like a cylinder for which the last combination it turns out to be adjacent to before.

 

12) Minimizzazione:

to)       the Map of Karnaugh of the escape function is come true and they characterize in it of the large blocks a how much possible for everyone of which at least bit must remain constant

b)       for every block one characterizes which are the bit of income that remain invariati and it makes them to meet in a And door after to have it denies them to you in the case had been of the 0.

c)       the escapes of all the And realized with the criterion of the point b) come made to meet in one door OR

An analogous minimizzazione can instead be obtained reasoning on the 0 that on the 1.

 

13) Display to 7 segments:

It is constituted from 7 diode valves LED having in common the cathode or the anode, the diode valves are illuminated when they are polarizes to you directly.

 

14) Realization of the pilotage of 3 display:

An only converter BCD is used/7 SEGMENTS for all and the three display, in fact taking advantage of the persistence of the eye it is had that the display they come periodically qualifies to you through a decoder whose given of income they are the same ones that they go on the incomes of having multiplexer 3 selection of â?"1 parallelism 4.