Diode valves, BJT, MOS and characteristics of the logical doors

Diode valve

1) Equation of the diode valve:

where V_D is the tension to the heads of the diode valve that for the etimologia of the word anode comes assumed positive on the same one, _{the D} is considered positive if it slides from the anode to the cathode, in the case instead the diode valve is polarized inversely, it is only covered from one inverse running weak person_{the S} directed from the cathode to the anode.

 

2) Models use you in order to represent the diode valve:

to)       ideal Diode valve  

It is had that for negative tensions the current that slides in the diode valve is 0 (…open circuit) while if in the diode valve whichever slides one positive current then the tension to its heads is 0 that is in this case it is introduced like a short circuit.

b)       ideal Diode valve with generator

For inferior tensions to the tension of threshold V_g @ 0,7V the current that slides in the diode valve is worth 0 while if in the diode valve whichever slides one positive current then the tension to its heads is V_g .

c)       Diode valve with resistances and generator

For a tension of inferior income to V_g the diode valve is equivalent to a resistance of value much elevated R_off while for a tension of advanced income to V_g the diode valve is equivalent to a resistance of value much low R_on having in series a generator of tension of equal largeness impressa to V_g , of the generator is towards the anode.

BJT

3) Equations of Ebers â " Moll and relative model  :

In order to write the equations it before convene to design the circuit of Ebers Moll, in particular reference to a BJT of type is made npn, and the anode in common is designed like the series of two having diode valves, everyone of they is crossed from one current that slides from the anode to the cathode and has in parallel a generator of current with opposite back respect to_{the D} and indicating how much of the current that crosses the other diode valve, catches up the opposite clip. Writing the equation of the currents it is to the collector clip who to the emettitore clip, obtains itself:

It is observed that in the practical realization to < < to_N in how much the region of emettitore it is contained to the inside of the base region and this is contained to the inside of the collector region therefore the transistor is asymmetric.

 

4) Theorem of reciprocity :

 

5) Relations between the polarizations of the splices and the modality of operation of the transistor:

JBE	JBC	Modality
Directed	Inverse	Direct assets
Inverse	Directed	Inverse assets
Directed	Directed	Saturation
Inverse	Inverse	Interdiction

 

6) Way of directed active operation :

The equations of Ebers can be become simpler - Moll in how much for the splice of emettitore polarized directly within parenthesis remains the single exponential term while for the splice of polarized collector inversely the exponential within parenthesis is negligible respect to 1, replacing the equation on the currents_and =_{C the B} obtains where is the static gain of current of the BJT.

For this modality of operation a linear model can also be defined that sees a generator of tension of value V_BE= 0.7V place between emettitore and base and a generator of current of value b_{Dthe B} situated between collector and base.

 

7) Way of inverse active operation :

The equations of Ebers can be become simpler - Moll in how much for the splice of collector polarized directly within parenthesis remains the single exponential term while for the polarized splice of emettitore inversely the exponential within parenthesis is negligible respect to 1. It is had that only one small part of the current iniettata from the base catches up the emettitore therefore is had to < < 1 the and also of it derives that all the current that reaches the collector comes from the base.

 

8) Way of operation of interdiction :

It is had that both the splices are polarized inversely, in the equations of Ebers â " Moll can be neglected esponenziali the respect to 1 in the parentesi is had therefore that the currents that cross the splices are infinitesimal and therefore the transistor can be assimilated to a opened switch, is in interdiction for V_BE < 0,65V.

 

9) Way of operation of saturation and relative simplified model:

In the equations of Ebers â " Moll the esponenziali within prevailing parentheses are respect to 1, elaborating them it obtains that therefore the current that slides in the collector in regimen of saturation is inferior to that it slides to you when it is polarized in active region, in particular has therefore comes used the parameter that indicates the level of saturation, in particular for s < 0,8 it is in saturation and V_CE < 0,2V while for s> 0,85 it is in active region and therefore V_{the CE} goes determined from the circuit. In the simplified model one has a generator of tension from 0,8V place between emettitore and base and a generator of tension of value 0,2V between collector and emettitore.

MOS

10) Effect of one applied increasing tension on the gate ones of a NMOS :

In a NMOS two drugged traps n are had and therefore the substrate is drugged p, a positive tension initially removes the gaps that are the majority bearers from the immediately below layer to oxide creating an emptying region, and in according to time it recalls the little minority bearers (…free electrons) present that therefore come to create a called layer of reversal channel, loads in present it is where is the ability to unit of surface of condenser MOS.

 

11) Effect of one positive tensionV _DS on transistor NMOS :

On condition that the channel is formed that is that _GS >V _T is hadV current will have in it the sliding of one_{the DS} which provokes one fallen of tension in the channel and therefore the tension along the channel is pure function of the coordinate like it is the value of loads with reversal to unit of surface multiplying for the W area of a section of the channel and for mobility m an expression for the current is obtained that crosses it that concurs to define the resistance differentiates them of channel for the generic one section at a distance x from the source and for a length dx from which integrating the relation is obtained that it expresses the current that slides between drain and source in function of the applied tensions where . The relation is valid for a NMOS that is not in saturation that is for which it has and , when instead the channel is to the limit between reversal and emptying while for the channel is choked to ridosso of the drain the situation that is obtained is equivalent to having a MOS to the limit between emptying and reversal but with a length of inferior channel, the tension applied to the heads of the channel to high resistance is much high one and that determines the passage of one constant current, is in region of saturation in how much_{the DS} is independent gives V_DS but depends solo from V_{the GS} .

 

12) Effect of the temperature on_{the DS} :

It is had that V_T diminishes of 2,5mV/°C to growing of the temperature while k _i effect diminishes in how much diminishes mobility of ibearers m this last one that is predominant.

 

Logical families

13) Meant of i symbols V_OL , V_OH , V , V_IH and relative relative operating conditions to the noise margins:

V_OL indicates the maximum tension of escape correspondent to the low level

V_OH indicates the minimal tension of escape correspondent to the high level

V the indicates the maximum tension of income that comes associated to the low level

V_IH indicates the minimal tension of income that comes associated to the high level

for the corrected operation of various connected doors entirety must be had V_OL < V and also V_OH > V_IH .

Based on the previous conditions the margins of noise e are defined that characterizes the noise amount that can be added to the income tension without to provoke an error.

 

14) Time of commutation:

It is the time necessary to pass from 10% of the value to regimen to 90% of the same one in the case is considering a transition from the level low to the high level while if a transition from the high level to the low level is being considered the time of commutation is the time necessary to pass from 90% to 10% of the value begins them. A lot important is a time that but it does not hold account of the time employed from the door in order to exceed the transitory one and to catch up 10%.

 

15) Delay of commutation:

It is the time that elapses between the moment in which the income it assumes 50% of its dynamics and the moment in which the same variation it appears on escape dynamics.

 

16) Dissipation of power in a digital circuit them:

where f_c is the frequency of job of the circuit while p_c is the probability that is a commutation while the ½ term is inserted because the commutation from H®L that it unloads the cargo condenser does not demand energy from the feeding.