Digital Analogic Conversion
1) Advantages of the numerical elaboration of mark them:
to) flexibility, not linear treatments are possible also and adapted you of it marks them
b) riproducibilità, the value of the members is a n° in a registry and therefore he remains constant in the time
c) to the vlves avoids uses it of members passes to you much large
d) it is not necessary to adapt circuits places in cascade
2) Disadvantages of the numerical elaboration of mark them:
to) it is necessary to otherwise implement of the blocks of conversion A/D e D/A absent
b) the theorem of the sampling limits the employment to the not highest frequencies
c) increases the power dissipated from the system
3) System of numerical elaboration of marks them:
It is constituted from a filter low-pass filter that it limits the band of marks them of income so as to to be able to apply the theorem of the sampling, follows a THA and a ADC that it sendes marks them digita them to a DSP which it carries out on it an elaboration and then it supplies it to a DAC that converts the data in the correspondent marks them analogic who for the sampling theorem is constituted from retorts of marks wished them therefore is necessary a pass-low filter.
4) THA:
A switch is a device constituted from operational a pursuer of tension having in series to the escape and in parallel to it a condenser isolated from the cargo by means of 2° operational a pursuer, following are had be:
to) Track, the circuit must follow the tension of income in faithful way therefore in short is behaved as an amplifier and in fact the detailed lists of the THA for this phase are those typical ones of an amplifier.
b) Hold, the circuit memorizza the value assumed from the income in the moment of passage from Track to Hold, can be introduced following not the idealità:
b1) Feedthrough, marks them of income is coupled with the ability also when the switch is opened in how much also in such condition it introduces not infinite stiffness.
B2) Droop, draft of the loss of is loaded from part of the condenser as a result of parasitic currents of varied nature
5) Characteristics of the THA in phase of transition Hold/Track:
Time of acquisition, is the time necessary to load the ability so that it chases marks them of endured income after that the passage from Hold to Track has been had.
6) Characteristics of the THA in phase of transition Track/Hold:
to) Settling Time, it is the time beyond which the transitory one reduces to one acceptable percentage
b) Inflation time of the switch, is the sum of a determinist delayq AP which had to the device and of the uncertainty of having openingh AP aleatory character.
7) ADC:
It is a device that partiziona the set of the tensions of income on the codes of escape according to the criterion of the rounding which the door to one characteristic of medium error to valor null.
8) Error of conversion:
It is the error that comes introduced from the
quantizzatore, if in fact it marks them from produced it comes sended
to an ideal DAC, what it obtains is marks them various from that one
in income to the quantizzatore, in particular bringing back such error
on the static characteristic of the converter looks at that it has a
course to rampa.e that segnale/rumore relationship SNR is given
from 
, therefore for every adopted bit in more in the
quantization has an improvement of 6dB of the segnale/rumore
relationship.
9) technical Detailed lists of the ADC:
to) Error of offset, it is the value of tension obtained from the intersection of the straight one of better approximation of the ADC with the income characteristic, can be compensated adding an opportune d.c. voltage to marks them of income.
b) Error of gain, has had to the fact that comes altered in uniform way the amplitude of how much of conversion, can be compensated multiplying marks them of income for an opportune gain.
c) Errors not linearity, has the integral linearity that is and the DNL that is linearity does not differentiate them
10) Typology of ADC:
to) flash
b) to successive approximations
c) to double rampa
11) Flash ADC:
The same one marks them of income comes sended to a bench of comparatori having like 2° income one of the tensions that can be obtained from a tension of reference by means of a resistivo Array constituted from resistances of R value except first and the last one that has R/2 value. If it marks them analogic is greater of the relative threshold to a comparatore supplies in escape a logical 1 otherwise 0, one is obtained therefore codifies said to thermometer that necessity of being converted coded railroad. Draft of a converter much fast one but has the defect that to growing of the n° of bit of quantization grows also the n° of comparatori and of resistances to insert therefore it increases the complexity of the circuit.
12) ADC to successive approximations:
We assume the realization of a 3 ADC to bit, has a shift register to ring constituted from 5 FFD, in it comes made to slide a 1, when it reaches the escape of 1° the FFD puts to 1 the set of the 1° of 3 FFSR whose exited they go to a DAC that supplies a tension that comes compared with the income tension, if it is to advanced it, the 1 must be carried to 0 and this happens tramite the connected income reset to the escape of one And having in income the escape of 2° the FFD and the escape of the comparatore. The escape of 2° the FFD goes also on the set of 2° the FFSR for which it is reasoned like before.
The escape of 5° the FFSR puts to 1 2° the income of the And that they have as 1° income the escape of the FFSR and therefore makes available in escape the binary data correspondent to the income.
13) ADC to double rampa:
An integrator realized with operational is had, it in one first integral phase the constant tension to quantizzare supplied from the THA, the tension that is obtained is negative and therefore compared with the mass it supplies a 1 logical one which it qualifies through a And the clock that it feeds a contatore to N 1 bit, when it places to 1 bit MSB, a shunter moves the income of the integrator on a negative tension of reference, therefore in escape a rampa is had to positive slope which reached 0v sends to 0 the escape of the comparatore that therefore blocks conteggio of the contatore supplying one codifies binary proporziona them to the income tension. The genius of this ADC resides in the fact that the defects of the condenser elidono in how much its characteristic is come taken advantage of in both the backs.
14) DAC to resistori hung to you:
To every bit of income it comes associated a resistance of value inversely proporziona them to a power of 2 so that to the MSB the lower resistance is associated and therefore slides in it the greater current. To second of the value of the bit an end of the resistances it is connected to a negative tension of positive reference or, while the 2° extreme of all resistance of feedback of R value is connected to the operational clip inverting of in inverting configuration having oneg and the positive clip to mass.
15) DAC to net R-2R:
We assume to realize a 3 DAC to bit, is had operational in configuration inverting with a resistance of feedback of value 3R, it has the positive clip to mass and the clip negative connected to a scale net R-2R in which the vertical resistances have value 2R and is connected to one second tension of negative positive reference or to of the state of the bit of the word converting in analogic.