Contatori sincroni

1)       Classes of logical circuits:

Class 0: Logical Combinatoria

Class 1: Logical Combinatoria memory

Class 2: Be successive and output depends on the state puts into effect them, not is incomes is the typical case of a contatore

Class 3: Is a machine of Moore in which the state puts into effect determines they the escape while the successive state is determined is from the incomes that give the state put into effect them

Class 4: Is a machine of Mealy in which the state they puts into effect and the incomes determine the successive state and the escape

 

2) general Shape of a circuit of Moore:

If 2^N are the states of which the process is formed, then they will have N Flip Flop whose exited they come is brought back to their incomes through one opportune combinatoria net that proposed in escape also in this case through one net combinatoria.che kinds the escape demanded in correspondence of every state.

 

3) Method of plan of a contatore sincrono:

to)       expressing in binary shape the numbers correspondents to the sequence that agrees to generate, every binary number corresponds to one be in kind assigns to every state the escape of a Flip Flop

b)       to create one Present table Been â " Next Been

c)       to choose a tipologia of Flip Flop and to write of the excitation table being held present that the FFD is what the study becomes simpler to the maximum and that the FFJK having much Don' t Beloveds in the excitation table is what more effective minimizzazione concurs one.

d)       To realize a K map for every income of the chosen FF it has on the aces the state word opportunely puts into effect subdivided them on the two aces and expressed coded Gray, to every intersection of this table one corresponds be puts into effect them, is gone in table PS-NS and it is looked at which it must be the NS, considering therefore a brace of bit to the time is entered in the table of excitation of the chosen FF and it is determined which income to the same one determines that transition of state, such value goes brought back in the K map which then must be diminished.

and)       the logical nets are come true that determine the incomes to the FF to leave from their escapes so as to to generate the sequence demanded from the system. Attention not to forget to connect clock to all a FF otherwise the system will remain always in the state begins them.

 

4) Shift Register:

It is with of FFD in which the escape of one it is connected to the income of the successive one in the chain, all but they are guides to you from the same one clock, are possible all the combinations of income parallel or seriale and escape parallel or seriale.

 

5) Ripple counter:

It is a contatore constituted from FFT you mail in cascade and having the same one clock, on the escape of the first one has a wave quadrant with the same frequency of the clock, on the escape of 2° the frequency is halved regarding the previous one and therefore via, the forehead comes called Ripple Counter in how much descendant of the clock moves like a wave on all the FF.

 

6) Ring Counter:

One obtains in such a way bringing back in income the escape of the last FF of the chain if a sequence in parallel is loaded and then it makes to shiftare with a clock obtains that the sequence after a n° of blows of clock equal to n° of the FF the filler in immutata escape.

 

7) Twisted Ring Counter:

It is a contatore in which the denied escape of the last FF of the chain is brought back in income to the first FF, in such a way it obtains that the ring is covered two times from the chain under shape of states 1 that are succeeded progressively and then of states 0.

 

8) Maximum Lenght Counter:

It is a FF chain in which the escapes of last the two they are the incomes of a Xor whose exited it comes brought back in income to the first FF, all the FF are feeds to you from the same one clock, obtains therefore one sequence of the maximum length.

 

9) UART:

Unyversal Asynchronous Receiver-Transmitter, is a having device a seriale income which words constituted from 1 bit of Start reach that normally is worth 0, 8 bit of data, 1 bit of parity (…are the Xor of the 8 bit previous) and two bit of Stop normally to 1 so that the successive data beginnings sure with one transition 1®0, all for a 11 total of bit. In short it is constituted from a Shift Register that comes loaded in seriale way to income SIN, when on this 1 0 comes found®a transition begins the conteggio of the 11 bit from part of an other contatore which to the end it supplies marks them Terminal Counter, the UART communicates to the processore that is a valid data in escape placing high RDY, when the processore wants to acquire it places high income RD of the UART which puts the data on the bus, to this point the processore after to have read it it places high RD and after a Pò it is had that the UART removes the data from the bus and puts high RDY.