Programmabili circuits for combinatoria logic

1) ROM:

It is a memory to single reading in which N incomes selects a lease of memory and in escape if of it it has its content. It is come true through a number of And doors to 2 equal incomes to the number of bit of data, ciascuna it has in income one of this bit while the other having income pu² to be put to 1 from decoder a N exited incomes and2 ^N.

 

2) Realization of one logical function by means of one matrix of diode valves:

One has decoder with N incomes that one of the 2 sends to the state high only^N exited, the escape function is come true with a resistore towards mass and of the diode valves that connect only the lines that interest to the aim of the determination of the logical function obtaining that it is to the high state only when the escape selected from the decoder is to connected it through a diode valve that comes therefore carried in conduction. The defect of this realization is that the decoder it must be in a position to supplying current to the diode valve in conduction, in alternative can be replaced every diode valve with a having MOS the gate ones piloted from the escape of decoder, moreover the source is to mass while the drain is connected to the line of escape of the logical function through one resistance towards the feeding.

 

3) PROM:

It is a programmabile ROM but a single time in short has a matrix of diode valves everyone of which has in series a fuse, during programming comes made to slide one current elevated in the contacts that do not interest breaking off the fuse in such a way.

 

4) EPROM:

It is a ROM that can be is programmed that cancelled, it is based on the MOS to gate floating or FAMOS, of the MOS equips you of two gate one of which is completely dipped in silicon oxide, sending in it of electrons through strafing with tensions elevated between the gate ones external and the channel obtains an elevation of the threshold tension, if this is raised beyond the value of the feeding, the result is that the channel will not be able to be never formed and therefore the MOS will be perennially interdetto. In order to cancel the content of the memory it is necessary to let out electrons from the gate ones inner that much energy through of the ultraviolet beams is possible supplying they.

 

5) EEPROM:

They are memories that can be cancelled electrically, come true by means of gate having FAMOS inner the much next one to the substrate therefore can be immettere and be extrapolated of the gate charges from inner for effect the Tunnel.

 

6) Flash Memories:

They are memories that concur the cancellation for via electrical worker of portions of memory and not necessarily of all the block, substantially are of the EEPROM and this greater satisfied selettività in terms of speed.

 

7) PLD:

Programmable Logic Devices. They are of the devices you to programmabile logic who concur to obtain one whichever logical function, in particular of it exist 4 typology : ROM, PAL, PLA, FPGA that are distinguished between they for the plan in which the programming happens, than for the ROM happen in the flat OR, for the PAL in the flat AND, for the PLA in both and the FPGA is the maximum of the versatilità.

 

8) PAL:

Programmed Array Logic. Draft of a device to programmabile logic in which an ended number of incomes is had and their complementary ones, then is an ended number of lines produced ognuna di.le which finishes on one And door. During programming one decides which incomes to connect which line produced to the aim to obtain the logical function or the wished logical functions, in particular for every logical function with of corresponding And doors come made to meet in one Or door.

 

9) PLA:

Programmable Logic Arrays. It is an elaborated device more regarding the PAL in how much concurs the programming of logic also in the flat Or therefore the escapes of the And that finish every produced line can be connected or less to one line of final escape also it on one And door with second of the wished function.

 

10) FPGA:

Field-Programmable Gate Array. Draft of a bidimensional Array of identical logical blocks surrounds you from vertical lines of connection and horizontal, everyone of the logical blocks pu² programmed being in order to generate a combinatorio logical circuit from 2 to 4 levels whose exited they can become the incomes of other logical blocks, in particular every logical block is constituted from a block dedicated to the functions of combinatoria logic, the multiplexer and the flip-flop.