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 Posted - 11/17/2005 : 08:37:51
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Maybe until now I did not understand many important things, for
example I've the famous
BlockRAM CORE v. 4.0 for it I choose to use the negative front 'cause
I use it in all the rest
of my circuit, the results in terms of speed are ok, almost 100MHz on
XCV1K-4 but in term of
simulation the result is really bad, it is :
# : WARNING: */RAMB4_S1 SETUP High VIOLATION ON ADDR(8) WITH RESPECT
TO CLK;
# : Expected := 0.01 ns; Observed := 0 ns; At : 1275 ns
# : Time: 1275 ns, Iteration: 3, Instance: /U1/U2/U2/B13.
# : WARNING: */RAMB4_S1 SETUP Low VIOLATION ON ADDR(7) WITH RESPECT TO
CLK;
# : Expected := 0.01 ns; Observed := 0 ns; At : 1275 ns
# : Time: 1275 ns, Iteration: 3, Instance: /U1/U2/U2/B13.
and really many other similar warnings, but let's try to understand
what the error say,
the problem is that the clock and the address change on the same time
while from data_sheets
seems that the address must arrive a little bit before 0.01ns.
The only rimedy I know is to change the operating edge of the ram so
now the address change on
negative edge of the clock and the ram work on positive edge. Now the
simulation it's ok but
the speed on FPGA is reduced to 45MHz.
Naturally I need 100MHz and a simulation working fine, it is possible
to obtain this ??
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Why not ?!? |
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 Posted - 11/19/2005 : 07:55:03
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> and really many other similar warnings, but let's try to understand
> what the error say,
> the problem is that the clock and the address change on the same time
> while from data_sheets
> seems that the address must arrive a little bit before 0.01ns.
Yes, a "little" bit more, so 2ns or so. ;-)
> The only rimedy I know is to change the operating edge of the ram so
> now the address change on
> negative edge of the clock and the ram work on positive edge. Now the
> simulation it's ok but
> the speed on FPGA is reduced to 45MHz.
This is clear, since the address changes on the negative edge and has so
only 1/2 clock cycle to propaget to the RAM. Switch back to te positive edge
and ignore the warning of the simulator. If you have a clean synchronous
design, just look at the timing analyzer, it will tell you how fast you can
go. |
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Joe
Status:
offline
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 Posted - 11/19/2005 : 08:01:49
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If you're running with a delay annotated netlist then you shouldn't be
getting any warnings. If you using the Xilinx mem timing models with
RTL then I could understand the warnings. You could make a non-timing
mem model for RTL sim or you could put a simulation delay in the
address lines that are ignored at synthesis. Something like
wire //synopsys translate_off
#1 //synopsys translate_on
slow_we=we;
Regards
p.s. I don't recommend going to negative edge to solve simulation
model issues.
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Edge selection with RAM
